Sensorian  1.0
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FXOS8700CQ.h
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20 
29 #ifndef __FXOS8700CQ_H__
30 #define __FXOS8700CQ_H__
31 
32 #include <stdint.h>
33 #include "MemoryMap.h"
34 
35 #define FXOS8700CQ_ADDRESS 0x1E
36 
37 /**************************STATUS Register********************************/
38 #define ZYXOW_MASK 0x80
39 #define ZOW_MASK 0x40
40 #define YOW_MASK 0x20
41 #define XOW_MASK 0x10
42 #define ZYXDR_MASK 0x08
43 #define ZDR_MASK 0x04
44 #define YDR_MASK 0x02
45 #define XDR_MASK 0x01
46 
47 /**************************STATUS Register********************************/
48 #define F_OVF_MASK 0x80
49 #define F_WMRK_FLAG_MASK 0x40
50 #define F_CNT5_MASK 0x20
51 #define F_CNT4_MASK 0x10
52 #define F_CNT3_MASK 0x08
53 #define F_CNT2_MASK 0x04
54 #define F_CNT1_MASK 0x02
55 #define F_CNT0_MASK 0x01
56 #define F_CNT_MASK 0x3F
57 
58 /**************************STATUS Register********************************/
59 #define OUT_X_MSB_REG 0x01
60 #define OUT_X_LSB_REG 0x02
61 #define OUT_Y_MSB_REG 0x03
62 #define OUT_Y_LSB_REG 0x04
63 #define OUT_Z_MSB_REG 0x05
64 #define OUT_Z_LSB_REG 0x06
65 
66 /**************************FIFO Register********************************/
67 #define F_MODE1_MASK 0x80
68 #define F_MODE0_MASK 0x40
69 #define F_WMRK5_MASK 0x20
70 #define F_WMRK4_MASK 0x10
71 #define F_WMRK3_MASK 0x08
72 #define F_WMRK2_MASK 0x04
73 #define F_WMRK1_MASK 0x02
74 #define F_WMRK0_MASK 0x01
75 #define F_MODE_MASK 0xC0
76 #define F_WMRK_MASK 0x3F
77 
78 #define F_MODE_DISABLED 0x00
79 #define F_MODE_CIRCULAR (F_MODE0_MASK)
80 #define F_MODE_FILL (F_MODE1_MASK)
81 #define F_MODE_TRIGGER (F_MODE1_MASK+F_MODE0_MASK)
82 
83 /**************************TRIG_CFG Register********************************/
84 #define TRIG_TRANS_MASK 0x20
85 #define TRIG_LNDPRT_MASK 0x10
86 #define TRIG_PULSE_MASK 0x08
87 #define TRIG_FF_MT_MASK 0x04
88 
89 /**************************SYSMOD Register********************************/
90 #define FGERR_MASK 0x80
91 #define FGT_4_MASK 0x40
92 #define FGT_3_MASK 0x20
93 #define FGT_2_MASK 0x10
94 #define FGT_1_MASK 0x08
95 #define FGT_0_MASK 0x04
96 #define FGT_MASK 0x7C
97 #define SYSMOD1_MASK 0x02
98 #define SYSMOD0_MASK 0x01
99 #define SYSMOD_MASK 0x03
100 
101 #define SYSMOD_STANDBY 0x00
102 #define SYSMOD_WAKE (SYSMOD0_MASK)
103 #define SYSMOD_SLEEP (SYSMOD1_MASK)
104 
105 /**************************INT_SOURCE Register********************************/
106 #define SRC_ASLP_MASK 0x80
107 #define SRC_FIFO_MASK 0x40
108 #define SRC_TRANS_MASK 0x20
109 #define SRC_LNDPRT_MASK 0x10
110 #define SRC_PULSE_MASK 0x08
111 #define SRC_FF_MT_MASK 0x04
112 #define SRC_DRDY_MASK 0x01
113 
114 /***********************WHO_AM_I Device ID Register****************************/
115 #define FXOS8700CQ 0xC7
116 #define MXOS8700CQ 0xC4
117 
118 /****************XYZ_DATA_CFG Sensor Data Configuration Register***************/
119 #define HPF_OUT_MASK 0x10 // MMA8451 and MMA8452 only
120 #define FS1_MASK 0x02
121 #define FS0_MASK 0x01
122 #define FS_MASK 0x03
123 
124 #define FULL_SCALE_2G 0x00
125 #define FULL_SCALE_4G (FS0_MASK)
126 #define FULL_SCALE_8G (FS1_MASK)
127 
128 
129 /************HP_FILTER_CUTOFF High Pass Filter Register **********************/
130 #define PULSE_HPF_BYP_MASK 0x20
131 #define PULSE_LPF_EN_MASK 0x10
132 #define SEL1_MASK 0x02
133 #define SEL0_MASK 0x01
134 #define SEL_MASK 0x03
135 
136 /*************PL_STATUS Portrait/Landscape Status Register *******************/
137 #define NEWLP_MASK 0x80
138 #define LO_MASK 0x40
139 #define LAPO1_MASK 0x04
140 #define LAPO0_MASK 0x02
141 #define BAFRO_MASK 0x01
142 #define LAPO_MASK 0x06
143 
144 
145 /************** PL_CFG Portrait/Landscape Configuration Register***************/
146 #define DBCNTM_MASK 0x80
147 #define PL_EN_MASK 0x40
148 
149 /*****PL_BF_ZCOMP Back/Front and Z Compensation Register***********************/
150 
151 #define BKFR1_MASK 0x80
152 #define BKFR0_MASK 0x40
153 #define ZLOCK2_MASK 0x04
154 #define ZLOCK1_MASK 0x02
155 #define ZLOCK0_MASK 0x01
156 #define BKFR_MASK 0xC0
157 #define ZLOCK_MASK 0x07
158 
159 /************PL_P_L_THS Portrait to Landscape Threshold Register***************/
160 #define PL_P_L_THS_REG 0x14
161 
162 #define P_L_THS4_MASK 0x80
163 #define P_L_THS3_MASK 0x40
164 #define P_L_THS2_MASK 0x20
165 #define P_L_THS1_MASK 0x10
166 #define P_L_THS0_MASK 0x08
167 #define HYS2_MASK 0x04
168 #define HYS1_MASK 0x02
169 #define HYS0_MASK 0x01
170 #define P_L_THS_MASK 0xF8
171 #define HYS_MASK 0x07
172 
173 /********************FF_MT_CFG Freefall and Motion Configuration Register******/
174 #define FF_MT_CFG_REG 0x15
175 
176 #define ELE_MASK 0x80
177 #define OAE_MASK 0x40
178 #define ZEFE_MASK 0x20
179 #define YEFE_MASK 0x10
180 #define XEFE_MASK 0x08
181 
182 /**********FF_MT_SRC Freefall and Motion Source Registers**********************/
183 #define FF_MT_SRC_REG 0x16
184 
185 #define EA_MASK 0x80
186 #define ZHE_MASK 0x20
187 #define ZHP_MASK 0x10
188 #define YHE_MASK 0x08
189 #define YHP_MASK 0x04
190 #define XHE_MASK 0x02
191 #define XHP_MASK 0x01
192 
193 /*****FF_MT_THS Freefall and Motion Threshold Registers*********************/
194 #define FT_MT_THS_REG 0x17
195 #define TRANSIENT_THS_REG 0x1F
196 
197 #define DBCNTM_MASK 0x80
198 #define THS6_MASK 0x40
199 #define THS5_MASK 0x20
200 #define THS4_MASK 0x10
201 #define THS3_MASK 0x08
202 #define THS2_MASK 0x04
203 #define TXS1_MASK 0x02
204 #define THS0_MASK 0x01
205 #define THS_MASK 0x7F
206 
207 
208 /********FF_MT_COUNT Freefall Motion Count Registers************************/
209 #define FF_MT_COUNT_REG 0x18
210 
211 /****************TRANSIENT_CFG Transient Configuration Register****************/
212 
213 #define TELE_MASK 0x10
214 #define ZTEFE_MASK 0x08
215 #define YTEFE_MASK 0x04
216 #define XTEFE_MASK 0x02
217 #define HPF_BYP_MASK 0x01
218 
219 /***********TRANSIENT_SRC Transient Source Register****************************/
220 
221 #define TEA_MASK 0x40
222 #define ZTRANSE_MASK 0x20
223 #define Z_TRANS_POL_MASK 0x10
224 #define YTRANSE_MASK 0x08
225 #define Y_TRANS_POL_MASK 0x04
226 #define XTRANSE_MASK 0x02
227 #define X_TRANS_POL_MASK 0x01
228 
229 
230 /**************************PULSE_CFG Register****************************/
231 
232 #define DPA_MASK 0x80
233 #define PELE_MASK 0x40
234 #define ZDPEFE_MASK 0x20
235 #define ZSPEFE_MASK 0x10
236 #define YDPEFE_MASK 0x08
237 #define YSPEFE_MASK 0x04
238 #define XDPEFE_MASK 0x02
239 #define XSPEFE_MASK 0x01
240 
241 
242 /**************************PULSE_SRC Register********************************/
243 
244 #define PEA_MASK 0x80
245 #define AXZ_MASK 0x40
246 #define AXY_MASK 0x20
247 #define AXX_MASK 0x10
248 #define DPE_MASK 0x08
249 #define POLZ_MASK 0x04
250 #define POLY_MASK 0x02
251 #define POLX_MASK 0x01
252 
253 #define PTHS_MASK 0x7F
254 
255 /***************CTRL_REG1 System Control 1 Register****************************/
256 #define ASLP_RATE1_MASK 0x80
257 #define ASLP_RATE0_MASK 0x40
258 #define DR2_MASK 0x20
259 #define DR1_MASK 0x10
260 #define DR0_MASK 0x08
261 #define LNOISE_MASK 0x04
262 #define FREAD_MASK 0x02
263 #define ACTIVE_MASK 0x01
264 #define ASLP_RATE_MASK 0xC0
265 #define DR_MASK 0x38
266 
267 #define ASLP_RATE_20MS 0x00
268 #define ASLP_RATE_80MS (ASLP_RATE0_MASK)
269 #define ASLP_RATE_160MS (ASLP_RATE1_MASK)
270 #define ASLP_RATE_640MS (ASLP_RATE1_MASK+ASLP_RATE0_MASK)
271 
272 #define ASLP_RATE_50HZ (ASLP_RATE_20MS)
273 #define ASLP_RATE_12_5HZ (ASLP_RATE_80MS)
274 #define ASLP_RATE_6_25HZ (ASLP_RATE_160MS)
275 #define ASLP_RATE_1_56HZ (ASLP_RATE_640MS)
276 
277 #define HYB_ASLP_RATE_25HZ (ASLP_RATE_20MS)
278 #define HYB_ASLP_RATE_6_25HZ (ASLP_RATE_80MS)
279 #define HYB_ASLP_RATE_1_56HZ (ASLP_RATE_160MS)
280 #define HYB_ASLP_RATE_0_8HZ (ASLP_RATE_640MS)
281 
282 #define DATA_RATE_1250US 0x00
283 #define DATA_RATE_2500US (DR0_MASK)
284 #define DATA_RATE_5MS (DR1_MASK)
285 #define DATA_RATE_10MS (DR1_MASK+DR0_MASK)
286 #define DATA_RATE_20MS (DR2_MASK)
287 #define DATA_RATE_80MS (DR2_MASK+DR0_MASK)
288 #define DATA_RATE_160MS (DR2_MASK+DR1_MASK)
289 #define DATA_RATE_640MS (DR2_MASK+DR1_MASK+DR0_MASK)
290 
291 #define DATA_RATE_800HZ (DATA_RATE_1250US)
292 #define DATA_RATE_400HZ (DATA_RATE_2500US)
293 #define DATA_RATE_200HZ (DATA_RATE_5MS)
294 #define DATA_RATE_100HZ (DATA_RATE_10MS)
295 #define DATA_RATE_50HZ (DATA_RATE_20MS)
296 #define DATA_RATE_12_5HZ (DATA_RATE_80MS)
297 #define DATA_RATE_6_25HZ (DATA_RATE_160MS)
298 #define DATA_RATE_1_56HZ (DATA_RATE_640MS)
299 
300 #define HYB_DATA_RATE_400HZ (DATA_RATE_1250US)
301 #define HYB_DATA_RATE_200HZ (DATA_RATE_2500US)
302 #define HYB_DATA_RATE_100HZ (DATA_RATE_5MS)
303 #define HYB_DATA_RATE_50HZ (DATA_RATE_10MS)
304 #define HYB_DATA_RATE_25HZ (DATA_RATE_20MS)
305 #define HYB_DATA_RATE_6_25HZ (DATA_RATE_80MS)
306 #define HYB_DATA_RATE_3_15HZ (DATA_RATE_160MS)
307 #define HYB_DATA_RATE_0_8HZ (DATA_RATE_640MS)
308 
309 #define ACTIVE (ACTIVE_MASK)
310 #define STANDBY 0x00
311 
312 /***************CTRL_REG2 System Control 2 Register****************************/
313 #define CTRL_REG2 0x2B
314 
315 #define ST_MASK 0x80
316 #define RST_MASK 0x40
317 #define SMODS1_MASK 0x10
318 #define SMODS0_MASK 0x08
319 #define SLPE_MASK 0x04
320 #define MODS1_MASK 0x02
321 #define MODS0_MASK 0x01
322 #define SMODS_MASK 0x18
323 #define MODS_MASK 0x03
324 
325 #define SMOD_NORMAL 0x00
326 #define SMOD_LOW_NOISE (SMODS0_MASK)
327 #define SMOD_HIGH_RES (SMODS1_MASK)
328 #define SMOD_LOW_POWER (SMODS1_MASK+SMODS0_MASK)
329 
330 #define MOD_NORMAL 0x00
331 #define MOD_LOW_NOISE (MODS0_MASK)
332 #define MOD_HIGH_RES (MODS1_MASK)
333 #define MOD_LOW_POWER (MODS1_MASK+MODS0_MASK)
334 
335 
336 /***************CTRL_REG3 System Control 3 Register****************************/
337 #define FIFO_GATE_MASK 0x80
338 #define WAKE_TRANS_MASK 0x40
339 #define WAKE_LNDPRT_MASK 0x20
340 #define WAKE_PULSE_MASK 0x10
341 #define WAKE_FF_MT_MASK 0x08
342 #define IPOL_MASK 0x02
343 #define PP_OD_MASK 0x01
344 
345 /***************CTRL_REG4 System Control 4 Register****************************/
346 #define INT_EN_ASLP_MASK 0x80
347 #define INT_EN_FIFO_MASK 0x40
348 #define INT_EN_TRANS_MASK 0x20
349 #define INT_EN_LNDPRT_MASK 0x10
350 #define INT_EN_PULSE_MASK 0x08
351 #define INT_EN_FF_MT_MASK 0x04
352 #define INT_EN_DRDY_MASK 0x01
353 
354 /***************CTRL_REG5 System Control 5 Register****************************/
355 #define INT_CFG_ASLP_MASK 0x80
356 #define INT_CFG_FIFO_MASK 0x40
357 #define INT_CFG_TRANS_MASK 0x20
358 #define INT_CFG_LNDPRT_MASK 0x10
359 #define INT_CFG_PULSE_MASK 0x08
360 #define INT_CFG_FF_MT_MASK 0x04
361 #define INT_CFG_DRDY_MASK 0x01
362 
363 /*
364 ** XYZ Offset Correction Registers
365 */
366 #define OFF_X_REG 0x2F
367 #define OFF_Y_REG 0x30
368 #define OFF_Z_REG 0x31
369 
370 /*
371 ** MAG CTRL_REG1 System Control 1 Register
372 */
373 #define M_ACAL_MASK 0x80
374 #define M_RST_MASK 0x40
375 #define M_OST_MASK 0x20
376 #define M_OSR2_MASK 0x10
377 #define M_OSR1_MASK 0x08
378 #define M_OSR0_MASK 0x04
379 #define M_HMS1_MASK 0x02
380 #define M_HMS0_MASK 0x01
381 #define M_OSR_MASK 0x1C
382 #define M_HMS_MASK 0x03
383 
384 //OSR Selections
385 #define M_OSR_1_56_HZ 0x00
386 #define M_OSR_6_25_HZ M_OSR0_MASK
387 #define M_OSR_12_5_HZ M_OSR1_MASK
388 #define M_OSR_50_HZ M_OSR1_MASK+M_OSR0_MASK
389 #define M_OSR_100_HZ M_OSR2_MASK
390 #define M_OSR_200_HZ M_OSR2_MASK+M_OSR0_MASK
391 #define M_OSR_400_HZ M_OSR2_MASK+M_OSR1_MASK
392 #define M_OSR_800_HZ M_OSR2_MASK+M_OSR1_MASK+M_OSR0_MASK
393 
394 //Hybrid Mode Selection
395 #define ACCEL_ACTIVE 0x00
396 #define MAG_ACTIVE M_HMS0_MASK
397 #define HYBRID_ACTIVE (M_HMS1_MASK | M_HMS0_MASK)
398 
399 /*
400 ** MAG CTRL_REG2 System Control 2 Register
401 */
402 
403 #define M_HYB_AUTOINC_MASK 0x20
404 #define M_MAXMIN_DIS_MASK 0x10
405 #define M_MAXMIN_DIS_THS_MASK 0x08
406 #define M_MAXMIN_RST_MASK 0x04
407 #define M_RST_CNT1_MASK 0x02
408 #define M_RST_CNT0_MASK 0x01
409 
410 //Mag Auto-Reset De-Gauss Frequency
411 #define RST_ODR_CYCLE 0x00
412 #define RST_16_ODR_CYCLE M_RST_CNT0_MASK
413 #define RST_512_ODR_CYCLE M_RST_CNT1_MASK
414 #define RST_DISABLED M_RST_CNT1_MASK+M_RST_CNT0_MASK
415 
416 /*
417 ** MAG CTRL_REG3 System Control 3 Register
418 */
419 
420 #define M_RAW_MASK 0x80
421 #define M_ASLP_OS_2_MASK 0x40
422 #define M_ASLP_OS_1_MASK 0x20
423 #define M_ASLP_OS_0_MASK 0x10
424 #define M_THS_XYZ_MASK 0x08
425 #define M_ST_Z_MASK 0x04
426 #define M_ST_XY1_MASK 0x02
427 #define M_ST_XY0_MASK 0x01
428 #define M_ASLP_OSR_MASK 0x70
429 #define M_ST_XY_MASK 0x03
430 
431 //OSR Selections
432 #define M_ASLP_OSR_1_56_HZ 0x00
433 #define M_ASLP_OSR_6_25_HZ M_ASLP_OS_0_MASK
434 #define M_ASLP_OSR_12_5_HZ M_ASLP_OS_1_MASK
435 #define M_ASLP_OSR_50_HZ M_ASLP_OS_1_MASK+M_ASLP_OS_0_MASK
436 #define M_ASLP_OSR_100_HZ M_ASLP_OS_2_MASK
437 #define M_ASLP_OSR_200_HZ M_ASLP_OS_2_MASK+M_ASLP_OS_0_MASK
438 #define M_ASLP_OSR_400_HZ M_ASLP_OS_2_MASK+M_ASLP_OS_1_MASK
439 #define M_ASLP_OSR_800_HZ M_ASLP_OS_2_MASK+M_ASLP_OS_1_MASK+M_ASLP_OS_0_MASK
440 
441 /*
442 ** MAG INT SOURCE Register
443 */
444 #define M_INT_SOURCE 0x5E
445 
446 #define SRC_M_DRDY_MASK 0x04
447 #define SRC_M_VECM_MASK 0x02
448 #define SRC_M_THS_MASK 0x01
449 
450 /*
451 ** ACCEL VECTOR CONFIG Register
452 */
453 
454 #define A_VECM_INIT_CFG_MASK 0x40
455 #define A_VECM_INIT_EN_MASK 0x20
456 #define A_VECM_WAKE_EN_MASK 0x10
457 #define A_VECM_EN_MASK 0x08
458 #define A_VECM_UPDM_MASK 0x04
459 #define A_VECM_INITM_MASK 0x02
460 #define A_VECM_ELE_MASK 0x01
461 
462 /*
463 ** ACCEL VECTOR THS MSB AND LSB Register
464 */
465 
466 #define A_VECM_DBCNTM_MASK 0x80
467 
468 /*
469 ** MAG VECTOR CONFIG Register
470 */
471 
472 #define M_VECM_INIT_CFG_MASK 0x40
473 #define M_VECM_INIT_EN_MASK 0x20
474 #define M_VECM_WAKE_EN_MASK 0x10
475 #define M_VECM_EN_MASK 0x08
476 #define M_VECM_UPDM_MASK 0x04
477 #define M_VECM_INITM_MASK 0x02
478 #define M_VECM_ELE_MASK 0x01
479 
480 /*
481 ** MAG VECTOR THS MSB AND LSB Register
482 */
483 
484 #define M_VECM_DBCNTM_MASK 0x80
485 
486 /*
487 ** ACCEL FFMT THS X MSB AND LSB Register
488 */
489 
490 #define A_FFMT_THS_XYZ_EN_MASK 0x80
491 #define A_FFMT_THS_X_LSB_MASK 0xFC
492 
493 /*
494 ** ACCEL FFMT THS Y MSB AND LSB Register
495 */
496 
497 #define A_FFMT_THS_Y_EN_MASK 0x80
498 #define A_FFMT_THS_Y_LSB_MASK 0xFC
499 
500 /*
501 ** ACCEL FFMT THS Z MSB AND LSB Register
502 */
503 
504 #define A_FFMT_THS_Z_EN_MASK 0x80
505 #define A_FFMT_THS_Z_LSB_MASK 0xFC
506 
507 #define FXOS8700CQ_WHOAMI_VAL 0xC7 // FXOS8700CQ WHOAMI production register value
508 #define FXOS8700CQ_READ_LEN 12 // 6 channels of two bytes = 12 bytes
509 #define UINT14_MAX 16383 // For processing the accelerometer data to right-justified 2's complement
510 
511 /***************************TYPES*********************************/
512 
516 typedef enum mode_t {DISABLED=0x00,
517  BUFFER=0x01,
518  OVERFLOW=0x10,
520 
524 typedef enum range_t {SCALE2G=0x00,
525  SCALE4G=0x01,
527 
528 
540 
544 typedef struct rawdata {
546  int16_t x;
547  int16_t y;
548  int16_t z;
550 } rawdata_t;
551 
552 void FXOS8700CQ_Initialize(void);
553 char FXOS8700CQ_ReadStatusReg(void);
554 void FXOS8700CQ_ActiveMode(void);
555 char FXOS8700CQ_StandbyMode(void);
556 void FXOS8700CQ_HybridMode(void);
557 char FXOS8700CQ_GetChipMode(void);
558 char FXOS8700CQ_ID (void);
559 
561 void FXOS8700CQ_PollAccelerometer (rawdata_t *accel_data);
562 void FXOS8700CQ_HighPassFilter(char status);
565 
567 void FXOS8700CQ_PollMagnetometer (rawdata_t *mag_data);
569 
570 void FXOS8700CQ_GetData(rawdata_t *accel_data, rawdata_t *magn_data);
571 
572 void FXOS8700CQ_FIFOMode(mode_t mode);
573 void FXOS8700CQ_SetODR (char DataRateValue);
574 char FXOS8700CQ_GetODR (void);
575 char FXOS8700CQ_GetTemperature(void);
576 
577 char FXOS8700CQ_GetOrientation(void);
582 
583 void FXOS8700CQ_WriteByte(char reg, char value);
584 void FXOS8700CQ_WriteByteArray(char reg, char* buffer, char value);
585 char FXOS8700CQ_ReadByte(char reg);
586 void FXOS8700CQ_ReadByteArray(char reg, char *buffer, unsigned int length);
587 
588 #endif
char FXOS8700CQ_GetTemperature(void)
Returns the silicon die chip temperature.
Definition: FXOS8700CQ.c:307
void FXOS8700CQ_FIFOMode(mode_t mode)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:273
char FXOS8700CQ_GetChipMode(void)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:106
void FXOS8700CQ_ConfigureOrientation(void)
Configure Orientation mode.
Definition: FXOS8700CQ.c:328
unsigned char buffer[256]
Definition: main.c:74
void FXOS8700CQ_ConfigureGenericTapMode(void)
Configure Single Tap mode.
Definition: FXOS8700CQ.c:444
void FXOS8700CQ_WriteByte(char reg, char value)
Writes a value to a register.
Definition: FXOS8700CQ.c:517
void FXOS8700CQ_WriteByteArray(char reg, char *buffer, char value)
Writes an array of bytes to the sensor.
Definition: FXOS8700CQ.c:529
void FXOS8700CQ_HighPassFilter(char status)
Enables or disables higpass filter on accelerometer data.
Definition: FXOS8700CQ.c:154
void FXOS8700CQ_HybridMode(void)
Configure the sensor in hybrid mode both the accelerometer and the magnetometer are active for data o...
Definition: FXOS8700CQ.c:91
char FXOS8700CQ_MagnetometerStatus(void)
Get magnetometer status.
Definition: FXOS8700CQ.c:228
Structure encapsulating triple axis raw data.
Definition: FXOS8700CQ.h:544
int16_t y
Definition: FXOS8700CQ.h:547
void FXOS8700CQ_ConfigureSingleTapMode(void)
Configure Single Tap mode.
Definition: FXOS8700CQ.c:467
void FXOS8700CQ_ConfigureAccelerometer(void)
Configure the accelerometer for data output.
Definition: FXOS8700CQ.c:126
int16_t x
Definition: FXOS8700CQ.h:546
void FXOS8700CQ_PollAccelerometer(rawdata_t *accel_data)
Accelerometer data is left justified.
Definition: FXOS8700CQ.c:140
void FXOS8700CQ_SetODR(char DataRateValue)
Set output data rate.
Definition: FXOS8700CQ.c:294
void FXOS8700CQ_ConfigureDoubleTapMode(void)
DoubleTap_LowPowerMode_NoLPF_400HzODR.
Definition: FXOS8700CQ.c:490
char FXOS8700CQ_ReadByte(char reg)
Starts up the sensor in Active mode.
Definition: FXOS8700CQ.c:539
void FXOS8700CQ_ActiveMode(void)
Starts up the sensor in Active mode.
Definition: FXOS8700CQ.c:69
Register memory map header.
void FXOS8700CQ_FullScaleRange(range_t range)
Configures the full scale range of the Accelerometer.
Definition: FXOS8700CQ.c:164
int16_t z
Definition: FXOS8700CQ.h:548
void FXOS8700CQ_ConfigureMagnetometer(void)
Configure the magnetometer for data output.
Definition: FXOS8700CQ.c:202
void FXOS8700CQ_PollMagnetometer(rawdata_t *mag_data)
Return the raw magnetometer data.
Definition: FXOS8700CQ.c:215
char FXOS8700CQ_ReadStatusReg(void)
Return the value of the status register.
Definition: FXOS8700CQ.c:60
range_t
Definition: FXOS8700CQ.h:524
void FXOS8700CQ_Initialize(void)
Initialize FXOS8700CQ, configure for an output rate of 200Hz with a +/- 2g scale. ...
Definition: FXOS8700CQ.c:42
void FXOS8700CQ_ReadByteArray(char reg, char *buffer, unsigned int length)
Read a number of contigous bytes from the chip.
Definition: FXOS8700CQ.c:551
mode_t
Definition: FXOS8700CQ.h:516
struct rawdata rawdata_t
Structure encapsulating triple axis raw data.
void FXOS8700CQ_SetAccelerometerDynamicRange(range_t range)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:174
char FXOS8700CQ_GetOrientation(void)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:318
void FXOS8700CQ_GetData(rawdata_t *accel_data, rawdata_t *magn_data)
Get raw data from both accelerometer and magnetometer.
Definition: FXOS8700CQ.c:240
char FXOS8700CQ_StandbyMode(void)
Starts up the sensor in Active mode.
Definition: FXOS8700CQ.c:79
char FXOS8700CQ_ID(void)
Returns the chip ID.
Definition: FXOS8700CQ.c:116
ACC_orientation_t
Definition: FXOS8700CQ.h:532
char FXOS8700CQ_GetODR(void)
Get output data rate.
Definition: FXOS8700CQ.c:282