Sensorian  1.0
C API Reference Guide Library
FXOS8700CQ.c
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20 
29 #include <unistd.h>
30 #include "FXOS8700CQ.h"
31 #include "MemoryMap.h"
32 #include "i2c.h"
33 
37 
42 void FXOS8700CQ_Initialize(void)
43 {
44  FXOS8700CQ_WriteByte(CTRL_REG2, RST_MASK); //Reset sensor, and wait for reboot to complete
45  bcm2835_delay(2); //Wait at least 1ms after issuing a reset before attempting communications.
46 
50  FXOS8700CQ_WriteByte(M_CTRL_REG2, M_HYB_AUTOINC_MASK); //Enable Hyb Mode Auto Increments in order to read all data
51  FXOS8700CQ_WriteByte(CTRL_REG4, INT_EN_DRDY_MASK ); // Enable interrupts for DRDY (TO, Aug 2012)
52  FXOS8700CQ_WriteByte(XYZ_DATA_CFG, FULL_SCALE_2G); //Full Scale of +/-2g
53  FXOS8700CQ_WriteByte(CTRL_REG1, (HYB_ASLP_RATE_25HZ|HYB_DATA_RATE_50HZ) ); //System Output Data Rate of 200Hz (5ms), Sleep Mode Poll Rate of 50Hz (20ms)
54 }
55 
60 char FXOS8700CQ_ReadStatusReg(void)
61 {
63 }
64 
69 void FXOS8700CQ_ActiveMode (void)
70 {
71  char reg1 = FXOS8700CQ_ReadByte(CTRL_REG1);
72  FXOS8700CQ_WriteByte(CTRL_REG1, (reg1 | ACTIVE_MASK)); //Set the Active bit in System Control 1 Register.
73 }
74 
79 char FXOS8700CQ_StandbyMode (void)
80 {
83  return (n & ~ACTIVE_MASK);
84 }
85 
91 void FXOS8700CQ_HybridMode(void)
92 {
94  FXOS8700CQ_WriteByte(M_CTRL_REG1, (HYBRID_ACTIVE|M_OSR2_MASK|M_OSR1_MASK|M_OSR0_MASK) ); // OSR=max, hybrid mode (TO, Aug 2012)
95  FXOS8700CQ_WriteByte(M_CTRL_REG2, M_HYB_AUTOINC_MASK); // enable hybrid autoinc
96  FXOS8700CQ_WriteByte(CTRL_REG4, INT_EN_DRDY_MASK ); // Enable interrupts for DRDY (TO, Aug 2012)
97  FXOS8700CQ_WriteByte(XYZ_DATA_CFG, FULL_SCALE_2G); // Set FSR of accel to +/-2g
100 }
101 
106 char FXOS8700CQ_GetChipMode(void)
107 {
108  char mode = FXOS8700CQ_ReadByte(SYSMOD);
109  return mode;
110 }
111 
116 char FXOS8700CQ_ID (void)
117 {
118  char id = FXOS8700CQ_ReadByte(WHO_AM_I);
119  return id;
120 }
121 
127 {
129  FXOS8700CQ_WriteByte(CTRL_REG4, INT_EN_DRDY_MASK ); // Enable interrupts for DRDY (TO, Aug 2012)
130  FXOS8700CQ_WriteByte(XYZ_DATA_CFG, FULL_SCALE_2G); // Set FSR of accel to +/-2g
133 }
134 
140 void FXOS8700CQ_PollAccelerometer (rawdata_t *accel_data)
141 {
142  char raw[6] = {0};
144  accel_data->x = (raw[0] << 8) | raw[1]; // Pull out 16-bit, 2's complement magnetometer data
145  accel_data->y = (raw[2] << 8) | raw[3];
146  accel_data->z = (raw[4] << 8) | raw[5];
147 }
148 
154 void FXOS8700CQ_HighPassFilter(char status)
155 {
157 }
158 
165 {
167 }
168 
175 {
177  switch(range)
178  {
179  case SCALE2G:
180  FXOS8700CQ_WriteByte(XYZ_DATA_CFG, (FXOS8700CQ_ReadByte(XYZ_DATA_CFG) & ~FS_MASK)); //Write the 2g dynamic range value into register 0x0E
181  break;
182  case SCALE4G:
183  FXOS8700CQ_WriteByte(XYZ_DATA_CFG, (FXOS8700CQ_ReadByte(XYZ_DATA_CFG) & ~FS_MASK)); //Write the 4g dynamic range value into register 0x0E
185  break;
186  case SCALE8G:
187  FXOS8700CQ_WriteByte(XYZ_DATA_CFG, (FXOS8700CQ_ReadByte(XYZ_DATA_CFG) & ~FS_MASK)); //Write the 8g dynamic range value into register 0x0E
189  break;
190 
191  default:
192 
193  break;
194  }
196 }
197 
203 {
205  FXOS8700CQ_WriteByte(M_CTRL_REG1, (HYBRID_ACTIVE|M_OSR2_MASK|M_OSR1_MASK|M_OSR0_MASK) ); // OSR=max, hybrid mode (TO, Aug 2012)
206  FXOS8700CQ_WriteByte(M_CTRL_REG2, M_HYB_AUTOINC_MASK); // enable hybrid autoinc
208 }
209 
215 void FXOS8700CQ_PollMagnetometer (rawdata_t *mag_data)
216 {
217  char raw[6] = {0};
219  mag_data->x = (raw[0] << 8) | raw[1]; // Return 16-bit, 2's complement magnetometer data
220  mag_data->y = (raw[2] << 8) | raw[3];
221  mag_data->z = (raw[4] << 8) | raw[5];
222 }
223 
229 {
230  char stat = FXOS8700CQ_ReadByte(M_DR_STATUS);
231  return stat;
232 }
233 
240 void FXOS8700CQ_GetData(rawdata_t *accel_data, rawdata_t *magn_data)
241 {
242  char raw[12] = {0};
244 
245  magn_data->x = (raw[0] << 8) | raw[1]; // Pull out 16-bit, 2's complement magnetometer data
246  magn_data->y = (raw[2] << 8) | raw[3];
247  magn_data->z = (raw[4] << 8) | raw[5];
248 
249  accel_data->x = (raw[6] << 8) | raw[7]; // Pull out 14-bit, 2's complement, right-justified accelerometer data
250  accel_data->y = (raw[8] << 8) | raw[9];
251  accel_data->z = (raw[10] << 8) | raw[11];
252 
253  // Have to apply corrections to make the int16_t correct
254  if(accel_data->x > UINT14_MAX/2)
255  {
256  accel_data->x -= UINT14_MAX;
257  }
258  if(accel_data->y > UINT14_MAX/2)
259  {
260  accel_data->y -= UINT14_MAX;
261  }
262  if(accel_data->z > UINT14_MAX/2)
263  {
264  accel_data->z -= UINT14_MAX;
265  }
266 }
267 
273 void FXOS8700CQ_FIFOMode(mode_t mode)
274 {
275  FXOS8700CQ_WriteByte(F_SETUP,6<<mode);
276 }
277 
282 char FXOS8700CQ_GetODR(void)
283 {
284  unsigned char odr = 0;
285 
286  return odr;
287 }
288 
294 void FXOS8700CQ_SetODR (char DataRateValue)
295 {
296  DataRateValue <<= 3; //Adjust the desired Output Data Rate value as needed.
298  FXOS8700CQ_WriteByte(CTRL_REG1,FXOS8700CQ_ReadByte(CTRL_REG1) & ~DR_MASK); //Write in the Data Rate value into Ctrl Reg 1
301 }
302 
307 char FXOS8700CQ_GetTemperature(void)
308 {
309  char temp = FXOS8700CQ_ReadByte(TEMP);
310 
311  return temp;
312 }
313 
318 char FXOS8700CQ_GetOrientation(void)
319 {
320  unsigned char orientation = FXOS8700CQ_ReadByte(PL_STATUS);
321  return orientation;
322 }
323 
329 {
330  unsigned char CTRL_REG1_Data = FXOS8700CQ_ReadByte(0x2A); //read contents of register
331  CTRL_REG1_Data &= 0xFE; //Set last bit to 0.
332  FXOS8700CQ_WriteByte(0x2A, CTRL_REG1_Data); //Write the updated value in CTRL_REG1 Put the part into Standby Mode
333 
334  //Set the data rate to 50 Hz (for example, but can choose any sample rate).
335 
336  CTRL_REG1_Data = FXOS8700CQ_ReadByte(0x2A); //Note: Can combine this step with above
337  CTRL_REG1_Data &= 0xC7; //Clear the sample rate bits
338  CTRL_REG1_Data |= 0x20; //Set the sample rate bits to 50 Hz
339  FXOS8700CQ_WriteByte(0x2A, CTRL_REG1_Data); //Write updated value into the register.
340 
341  //Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection.
342  unsigned char PLCFG_Data = FXOS8700CQ_ReadByte (0x11);
343  PLCFG_Data |= 0x40;
344  FXOS8700CQ_WriteByte(0x11, PLCFG_Data);
345 
346  // Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet.
347 
348  unsigned char PL_BF_ZCOMP_Data = FXOS8700CQ_ReadByte(0x13);
349  PL_BF_ZCOMP_Data &= 0x3F; //Clear bit 7 and 6
350  //Select one of the following to set the B/F angle value:
351  PL_BF_ZCOMP_Data |= 0x00; // This does nothing additional and keeps bits [7:6] = 00
352  PL_BF_ZCOMP_Data |= 0x40; // Sets bits[7:6] = 01
353  PL_BF_ZCOMP_Data |= 0x80; // Sets bits[7:6] = 02
354  PL_BF_ZCOMP_Data |= 0xC0; // Sets bits[7:6] = 03
355  FXOS8700CQ_WriteByte(0x13, PL_BF_ZCOMP_Data); //Write in the updated Back/Front Angle
356  //Set the Z-Lockout angle trip point in register 0x13 following the table in datasheet
357  PL_BF_ZCOMP_Data = FXOS8700CQ_ReadByte(0x1C); //Read out contents of the register (can be read by all
358  PL_BF_ZCOMP_Data &= 0xF8; //Clear the last three bits of the register
359  PL_BF_ZCOMP_Data |= 0x00; //This does nothing additional but the Z-lockout selection will remain at 14°
360  //PL_BF_ZCOMP_Data | = 0x01; //Set the Z-lockout angle to 18°
361  //PL_BF_ZCOMP_Data | = 0x02; //Set the Z-lockout angle to 21°
362  //PL_BF_ZCOMP_Data | = 0x03; //Set the Z-lockout angle to 25°
363  //PL_BF_ZCOMP_Data | = 0x04; //Set the Z-lockout angle to 29°
364  //PL_BF_ZCOMP_Data | = 0x05; //Set the Z-lockout angle to 33°
365  //PL_BF_ZCOMP_Data | = 0x06; //Set the Z-lockout angle to 37°
366  //PL_BF_ZCOMP_Data | = 0x07; //Set the Z-lockout angle to 42°
367  FXOS8700CQ_WriteByte(0x13, PL_BF_ZCOMP_Data); //Write in the updated Z-lockout angle
368 
369  //Set the Trip Threshold Angle
370  //NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the MMA8451Q.
371 
372  unsigned char P_L_THS_Data = FXOS8700CQ_ReadByte(0x14); //(can be read by all versions of MMA845xQ) //The remaining parts of this step only apply to MMA8451Q
373  P_L_THS_Data &= 0x07; //Clear the Threshold values
374 
375  //Choose one of the following options
376  P_L_THS_Data |= (0x07)<<3; //Set Threshold to 15°
377  //P_L_THS_Data | = (0x09)<<3; //Set Threshold to 20°
378  //P_L_THS_Data | = (0x0C)<<3; //Set Threshold to 30°
379  //P_L_THS_Data | = (0x0D)<<3; //Set Threshold to 35°
380  //P_L_THS_Data | = (0x0F)<<3; //Set Threshold to 40°
381  //P_L_THS_Data | = (0x10)<<3; //Set Threshold to 45°
382  //P_L_THS_Data | = (0x13)<<3; //Set Threshold to 55°
383  //P_L_THS_Data | = (0x14)<<3; //Set Threshold to 60°
384  //P_L_THS_Data | = (0x17)<<3; //Set Threshold to 70°
385  //P_L_THS_Data | = (0x19)<<3; //Set Threshold to 75°
386  FXOS8700CQ_WriteByte(0x14,P_L_THS_Data);
387 
388  // Set the Hysteresis Angle
389  P_L_THS_Data = FXOS8700CQ_ReadByte(0x14);
390  //NOTE: The remaining parts of this step only apply to the MMA8451Q.
391  P_L_THS_Data &= 0xF8;//Clear the Hysteresis values
392  //P_L_THS_Data | = 0x01; //Set Hysteresis to ±4°
393  P_L_THS_Data |= 0x02;//Set Threshold to ±7°
394  //P_L_THS_Data | = 0x03;//Set Threshold to ±11°
395  //P_L_THS_Data | = 0x04;//Set Threshold to ±14°
396  //P_L_THS_Data | = 0x05;//Set Threshold to ±17°
397  //P_L_THS_Data | = 0x06; //Set Threshold to ±21°
398  //P_L_THS_Data | = 0x07; //Set Threshold to ±24°
399  FXOS8700CQ_WriteByte(0x14,P_L_THS_Data);
400 
401  //Register 0x2D, Control Register 4 configures all embedded features for interrupt detection.
402  /*
403  To set this device up to run an interrupt service routine:
404  Program the Orientation Detection bit in Control Register 4.
405  Set bit 4 to enable the orientation detection “INT_EN_LNDPRT”.
406  */
407  unsigned char CTRL_REG4_Data = FXOS8700CQ_ReadByte(0x2D); //Read out the contents of the register
408  CTRL_REG4_Data |= 0x10; //Set bit 4
409  FXOS8700CQ_WriteByte(0x2D, CTRL_REG4_Data); //Set the bit and write into CTRL_REG4
410 
411 
412  // Register 0x2E is Control Register 5 which gives the option of routing the interrupt to either INT1 or INT2
413  /*
414  Depending on which interrupt pin is enabled and configured to the processor:
415  Set bit 4 “INT_CFG_LNDPRT” to configure INT1, or,
416  Leave the bit clear to configure INT2.
417  */
418 
419  unsigned char CTRL_REG5_Data = FXOS8700CQ_ReadByte(0x2E); //In the next two lines choose to clear bit 4 to route to INT2 or set bit 4 to route to INT1
420  CTRL_REG5_Data &= 0xEF; //Clear bit 4 to choose the interrupt to route to INT2
421  CTRL_REG5_Data |= 0x10; //Set bit 4 to choose the interrupt to route to INT1
422  FXOS8700CQ_WriteByte(0x2E, CTRL_REG5_Data); //Write in the interrupt routing selection
423 
424  // Set the debounce counter in register 0x12
425  /*
426  This value will scale depending on the application-specific required ODR.
427  If the device is set to go to sleep, reset the debounce counter before the device goes to sleep. This setting
428  helps avoid long delays since the debounce will always scale with the current sample rate. The debounce
429  can be set between 50 ms - 100 ms to avoid long delays.
430  */
431  FXOS8700CQ_WriteByte(0x12, 0x05);//This sets the debounce counter to 100 ms at 50 Hz
432 
433  //Put the device in Active Mode
434  CTRL_REG1_Data = FXOS8700CQ_ReadByte(0x2A);//Read out the contents of the register
435  CTRL_REG1_Data |= 0x01;//Change the value in the register to Active Mode.
436  FXOS8700CQ_WriteByte(0x2A, CTRL_REG1_Data);//Write in the updated value to put the device in Active Mode
437 
438 }
439 
445 {
446  FXOS8700CQ_WriteByte(PULSE_CFG, 0x55); //Example X, Y and Z configured for Single Tap with Latch enabled
447  //FXOS8700CQ_WriteByte(PULSE_CFG, 0x6A); //Example X, Y and Z configured for Double Tap with Latch enabled
448  //FXOS8700CQ_WriteByte(PULSE_CFG, 0x7F); //Example X, Y and Z configured for Single Tap and Double Tap with Latch enabled
449 
450  /**************Set Threesholds*************************/
451  FXOS8700CQ_WriteByte(PULSE_THSX, 0x20); //Set X Threshold to 32 counts or 2g
452  FXOS8700CQ_WriteByte(PULSE_THSY, 0x20); //Set Y Threshold to 32 counts or 2g
453  FXOS8700CQ_WriteByte(PULSE_THSZ, 0x0C); //Set Z Threshold to 48 counts or 3g
454 
455  FXOS8700CQ_WriteByte(PULSE_TMLT, 0x06); //Set the Pulse Time Limit for 30 ms at 200 Hz ODR in Normal Mode with the LPF Enabled A. 30 ms/5 ms = 6 counts
456  FXOS8700CQ_WriteByte(PULSE_LTCY, 0x28); //Set the Pulse Latency Timer to 200 ms, 200 Hz ODR Low Power Mode, LPF Not Enabled. 200 ms/5.0 ms = 40 counts
457  FXOS8700CQ_WriteByte(PULSE_WIND, 0x0F); //Set the Pulse window to 300 ms, 100 Hz ODR Low Power Mode, LPF Enabled 300 ms/20 ms = 15 counts
458 
459  FXOS8700CQ_WriteByte(CTRL_REG4, 0x08); //Enable Tap Interrupt in Register 0x2D.
460  FXOS8700CQ_WriteByte(CTRL_REG5,0x08); //Set Tap to INT1
461 }
462 
468 {
469  //To set up any configuration make sure to be in Standby Mode.
470 
471  FXOS8700CQ_WriteByte(CTRL_REG1, 0x08); //400 Hz, Standby Mode
472  FXOS8700CQ_WriteByte(PULSE_CFG, 0x15); //Enable X and Y and Z Single Pulse
473  FXOS8700CQ_WriteByte(PULSE_THSX, 0x19); //Set X Threshold to 1.575g
474  FXOS8700CQ_WriteByte(PULSE_THSY, 0x19); //Set Y Threshold to 1.575g
475  FXOS8700CQ_WriteByte(PULSE_THSZ, 0x2A); //Set Z Threshold to 2.65g
476  FXOS8700CQ_WriteByte(PULSE_TMLT,0x50); //Set Time Limit for Tap Detection to 50 ms, Normal Mode, No LPF
477  FXOS8700CQ_WriteByte(PULSE_LTCY,0xF0); // Set Latency Time to 300 ms
478  FXOS8700CQ_WriteByte(CTRL_REG4, 0x08); //Route INT1 to System
479  FXOS8700CQ_WriteByte(CTRL_REG5, 0x08); //Route Pulse Interrupt Block to INT1 hardware Pin
480  unsigned char CTRL_REG1_Data = FXOS8700CQ_ReadByte(CTRL_REG1); //Read out the contents of the register
481  CTRL_REG1_Data |= 0x01; //Change the value in the register to Active Mode.
482 
483  FXOS8700CQ_WriteByte(CTRL_REG1, CTRL_REG1_Data); //Write in the updated value to put the device in
484 }
485 
491 {
492  FXOS8700CQ_WriteByte(CTRL_REG1, 0x08); //400 Hz, Standby Mode
493  FXOS8700CQ_WriteByte(PULSE_CFG, 0x2A); //Enable X, Y and Z Double Pulse with DPA = 0 no double pulse abort
494  FXOS8700CQ_WriteByte(PULSE_THSX, 0x08); //Set X Threshold to 3g
495  FXOS8700CQ_WriteByte(PULSE_THSY, 0x08); //Set Y Threshold to 3g
496  FXOS8700CQ_WriteByte(PULSE_THSZ, 0x03); //Set Z Threshold to 5g
497  FXOS8700CQ_WriteByte(PULSE_TMLT,0x30); //60 ms Note: 400 Hz ODR, Time step is 1.25 ms per step
498  FXOS8700CQ_WriteByte(PULSE_LTCY,0x50); //200 ms Set Latency Time to 200 ms
499  FXOS8700CQ_WriteByte(PULSE_WIND,0x78); //300 ms Set Time Window for second tap to 300 ms
500  FXOS8700CQ_WriteByte(CTRL_REG4, 0x08); //Enable Pulse Interrupt in System CTRL_REG4
501  FXOS8700CQ_WriteByte(CTRL_REG5, 0x08); //Route Pulse Interrupt to INT1 hardware Pin CTRL_REG5
502 
503  unsigned char CTRL_REG1_Data = FXOS8700CQ_ReadByte(CTRL_REG1); //Read out the contents of the register
504  CTRL_REG1_Data |= 0x01; //Change the value in the register to Active Mode.
505 
506  FXOS8700CQ_WriteByte(CTRL_REG1, CTRL_REG1_Data); //Write in the updated value to put the device in Active Mode.
507 }
508 
510 
517 void FXOS8700CQ_WriteByte(char reg, char value)
518 {
519  I2C_WriteByteRegister(reg,value); //Write value to register
520 }
521 
529 void FXOS8700CQ_WriteByteArray(char reg, char* buffer, char length)
530 {
531  I2C_WriteByteArray(reg,buffer,length); //Write values to register
532 }
533 
539 char FXOS8700CQ_ReadByte(char reg)
540 {
541  return I2C_ReadByteRegister(reg); //Read register current value
542 }
543 
551 void FXOS8700CQ_ReadByteArray(char reg, char *buffer, unsigned int length)
552 {
553  I2C_ReadByteArray(reg,buffer,length); //Read values starting from the reg address
554 }
#define M_CTRL_REG1
Definition: MemoryMap.h:117
#define INT_EN_DRDY_MASK
Definition: FXOS8700CQ.h:352
char FXOS8700CQ_GetTemperature(void)
Returns the silicon die chip temperature.
Definition: FXOS8700CQ.c:307
void FXOS8700CQ_FIFOMode(mode_t mode)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:273
#define PULSE_TMLT
Definition: MemoryMap.h:64
#define TEMP
Definition: MemoryMap.h:107
char FXOS8700CQ_GetChipMode(void)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:106
void FXOS8700CQ_ConfigureOrientation(void)
Configure Orientation mode.
Definition: FXOS8700CQ.c:328
#define ACTIVE_MASK
Definition: FXOS8700CQ.h:263
unsigned char buffer[256]
Definition: main.c:74
void FXOS8700CQ_ConfigureGenericTapMode(void)
Configure Single Tap mode.
Definition: FXOS8700CQ.c:444
#define PULSE_THSX
Definition: MemoryMap.h:61
void FXOS8700CQ_ReadByteArray(char reg, char *buffer, unsigned int length)
Read a number of contigous bytes from the chip.
Definition: FXOS8700CQ.c:551
void FXOS8700CQ_HighPassFilter(char status)
Enables or disables higpass filter on accelerometer data.
Definition: FXOS8700CQ.c:154
#define SYSMOD
Definition: MemoryMap.h:41
void FXOS8700CQ_HybridMode(void)
Configure the sensor in hybrid mode both the accelerometer and the magnetometer are active for data o...
Definition: FXOS8700CQ.c:91
char FXOS8700CQ_MagnetometerStatus(void)
Get magnetometer status.
Definition: FXOS8700CQ.c:228
#define PULSE_THSZ
Definition: MemoryMap.h:63
#define M_CTRL_REG2
Definition: MemoryMap.h:118
#define STATUS
Definition: MemoryMap.h:32
Structure encapsulating triple axis raw data.
Definition: FXOS8700CQ.h:544
int16_t y
Definition: FXOS8700CQ.h:547
#define XYZ_DATA_CFG
Definition: MemoryMap.h:44
#define FXOS8700CQ_READ_LEN
Definition: FXOS8700CQ.h:508
void FXOS8700CQ_ConfigureSingleTapMode(void)
Configure Single Tap mode.
Definition: FXOS8700CQ.c:467
void FXOS8700CQ_ConfigureAccelerometer(void)
Configure the accelerometer for data output.
Definition: FXOS8700CQ.c:126
void I2C_WriteByteArray(char reg, char *data, unsigned int length)
Writes a buffer array to the registers.
Definition: i2c.c:100
#define UINT14_MAX
Definition: FXOS8700CQ.h:509
void FXOS8700CQ_WriteByteArray(char reg, char *buffer, char length)
Writes an array of bytes to the sensor.
Definition: FXOS8700CQ.c:529
#define FULL_SCALE_8G
Definition: FXOS8700CQ.h:126
int16_t x
Definition: FXOS8700CQ.h:546
#define FS_MASK
Definition: FXOS8700CQ.h:122
#define OUT_X_MSB
Definition: MemoryMap.h:33
#define M_OSR0_MASK
Definition: FXOS8700CQ.h:378
#define WHO_AM_I
Definition: MemoryMap.h:43
void FXOS8700CQ_PollAccelerometer(rawdata_t *accel_data)
Accelerometer data is left justified.
Definition: FXOS8700CQ.c:140
void FXOS8700CQ_SetODR(char DataRateValue)
Set output data rate.
Definition: FXOS8700CQ.c:294
#define CTRL_REG2
Definition: FXOS8700CQ.h:313
#define CTRL_REG5
Definition: MemoryMap.h:72
void FXOS8700CQ_ConfigureDoubleTapMode(void)
DoubleTap_LowPowerMode_NoLPF_400HzODR.
Definition: FXOS8700CQ.c:490
void I2C_WriteByteRegister(unsigned char reg, unsigned char data)
Writes a byte value to a register address.
Definition: i2c.c:66
#define M_OSR1_MASK
Definition: FXOS8700CQ.h:377
#define M_OUT_X_MSB
Definition: MemoryMap.h:77
void FXOS8700CQ_ActiveMode(void)
Starts up the sensor in Active mode.
Definition: FXOS8700CQ.c:69
void FXOS8700CQ_FullScaleRange(range_t range)
Configures the full scale range of the Accelerometer.
Definition: FXOS8700CQ.c:164
#define CTRL_REG4
Definition: MemoryMap.h:71
int16_t z
Definition: FXOS8700CQ.h:548
#define HYB_DATA_RATE_50HZ
Definition: FXOS8700CQ.h:303
#define PL_STATUS
Definition: MemoryMap.h:46
void FXOS8700CQ_ConfigureMagnetometer(void)
Configure the magnetometer for data output.
Definition: FXOS8700CQ.c:202
void FXOS8700CQ_PollMagnetometer(rawdata_t *mag_data)
Return the raw magnetometer data.
Definition: FXOS8700CQ.c:215
#define HYBRID_ACTIVE
Definition: FXOS8700CQ.h:397
#define RST_MASK
Definition: FXOS8700CQ.h:316
char FXOS8700CQ_ReadStatusReg(void)
Return the value of the status register.
Definition: FXOS8700CQ.c:60
range_t
Definition: FXOS8700CQ.h:524
#define PULSE_CFG
Definition: MemoryMap.h:59
#define DR_MASK
Definition: FXOS8700CQ.h:265
void FXOS8700CQ_Initialize(void)
Initialize FXOS8700CQ, configure for an output rate of 200Hz with a +/- 2g scale. ...
Definition: FXOS8700CQ.c:42
I2C driver header.
#define M_HYB_AUTOINC_MASK
Definition: FXOS8700CQ.h:403
#define CTRL_REG1
Definition: MemoryMap.h:68
char FXOS8700CQ_ReadByte(char reg)
Starts up the sensor in Active mode.
Definition: FXOS8700CQ.c:539
mode_t
Definition: FXOS8700CQ.h:516
#define M_OSR2_MASK
Definition: FXOS8700CQ.h:376
void FXOS8700CQ_SetAccelerometerDynamicRange(range_t range)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:174
#define FULL_SCALE_4G
Definition: FXOS8700CQ.h:125
char FXOS8700CQ_GetOrientation(void)
Returns current mode of the chip.
Definition: FXOS8700CQ.c:318
#define PULSE_WIND
Definition: MemoryMap.h:66
unsigned char I2C_ReadByteRegister(char reg)
Reads a byte from a register.
Definition: i2c.c:122
#define PULSE_THSY
Definition: MemoryMap.h:62
#define PULSE_LTCY
Definition: MemoryMap.h:65
void FXOS8700CQ_WriteByte(char reg, char value)
Writes a value to a register.
Definition: FXOS8700CQ.c:517
#define FULL_SCALE_2G
Definition: FXOS8700CQ.h:124
Register memory map header.
void FXOS8700CQ_GetData(rawdata_t *accel_data, rawdata_t *magn_data)
Get raw data from both accelerometer and magnetometer.
Definition: FXOS8700CQ.c:240
char FXOS8700CQ_StandbyMode(void)
Starts up the sensor in Active mode.
Definition: FXOS8700CQ.c:79
void I2C_ReadByteArray(char reg, char *buffer, unsigned int length)
Initializes the I2C peripheral.
Definition: i2c.c:138
#define F_SETUP
Definition: MemoryMap.h:39
char FXOS8700CQ_ID(void)
Returns the chip ID.
Definition: FXOS8700CQ.c:116
#define HYB_ASLP_RATE_25HZ
Definition: FXOS8700CQ.h:277
#define M_DR_STATUS
Definition: MemoryMap.h:76
char FXOS8700CQ_GetODR(void)
Get output data rate.
Definition: FXOS8700CQ.c:282