FXOS8700CQ.h

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/****************************************************************************
 * Copyright (C) 2015 Sensorian
 *                                                                          *
 * This file is part of Sensorian.                                          *
 *                                                                          *
 *   Sensorian is free software: you can redistribute it and/or modify it   *
 *   under the terms of the GNU Lesser General Public License as published  *
 *   by the Free Software Foundation, either version 3 of the License, or   *
 *   (at your option) any later version.                                    *
 *                                                                          *
 *   Sensorian is distributed in the hope that it will be useful,           *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of         *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the          *
 *   GNU Lesser General Public License for more details.                    *
 *                                                                          *
 *   You should have received a copy of the GNU Lesser General Public       *
 *   License along with Sensorian.                                          *
 *   If not, see <http://www.gnu.org/licenses/>.                            *
 ****************************************************************************/
 
#ifndef __FXOS8700CQ_H__
#define __FXOS8700CQ_H__

#include <stdint.h>
#include "MemoryMap.h"

#define FXOS8700CQ_ADDRESS    0x1E

/**************************STATUS Register********************************/
#define ZYXOW_MASK            0x80
#define ZOW_MASK              0x40
#define YOW_MASK              0x20
#define XOW_MASK              0x10
#define ZYXDR_MASK            0x08
#define ZDR_MASK              0x04
#define YDR_MASK              0x02
#define XDR_MASK              0x01

/**************************STATUS Register********************************/
#define F_OVF_MASK            0x80
#define F_WMRK_FLAG_MASK      0x40
#define F_CNT5_MASK           0x20
#define F_CNT4_MASK           0x10
#define F_CNT3_MASK           0x08
#define F_CNT2_MASK           0x04
#define F_CNT1_MASK           0x02
#define F_CNT0_MASK           0x01
#define F_CNT_MASK            0x3F

/**************************STATUS Register********************************/
#define OUT_X_MSB_REG         0x01
#define OUT_X_LSB_REG         0x02
#define OUT_Y_MSB_REG         0x03
#define OUT_Y_LSB_REG         0x04
#define OUT_Z_MSB_REG         0x05
#define OUT_Z_LSB_REG         0x06

/**************************FIFO Register********************************/
#define F_MODE1_MASK          0x80
#define F_MODE0_MASK          0x40
#define F_WMRK5_MASK          0x20
#define F_WMRK4_MASK          0x10
#define F_WMRK3_MASK          0x08
#define F_WMRK2_MASK          0x04
#define F_WMRK1_MASK          0x02
#define F_WMRK0_MASK          0x01
#define F_MODE_MASK           0xC0
#define F_WMRK_MASK           0x3F

#define F_MODE_DISABLED       0x00
#define F_MODE_CIRCULAR       (F_MODE0_MASK)
#define F_MODE_FILL           (F_MODE1_MASK)
#define F_MODE_TRIGGER        (F_MODE1_MASK+F_MODE0_MASK)

/**************************TRIG_CFG Register********************************/
#define TRIG_TRANS_MASK       0x20
#define TRIG_LNDPRT_MASK      0x10
#define TRIG_PULSE_MASK       0x08
#define TRIG_FF_MT_MASK       0x04

/**************************SYSMOD Register********************************/
#define FGERR_MASK            0x80    
#define FGT_4_MASK            0x40    
#define FGT_3_MASK            0x20    
#define FGT_2_MASK            0x10    
#define FGT_1_MASK            0x08    
#define FGT_0_MASK            0x04    
#define FGT_MASK              0x7C    
#define SYSMOD1_MASK          0x02
#define SYSMOD0_MASK          0x01
#define SYSMOD_MASK           0x03

#define SYSMOD_STANDBY        0x00
#define SYSMOD_WAKE           (SYSMOD0_MASK)
#define SYSMOD_SLEEP          (SYSMOD1_MASK)

/**************************INT_SOURCE Register********************************/
#define SRC_ASLP_MASK         0x80
#define SRC_FIFO_MASK         0x40    
#define SRC_TRANS_MASK        0x20
#define SRC_LNDPRT_MASK       0x10
#define SRC_PULSE_MASK        0x08
#define SRC_FF_MT_MASK        0x04
#define SRC_DRDY_MASK         0x01

/***********************WHO_AM_I Device ID Register****************************/
#define FXOS8700CQ            0xC7
#define MXOS8700CQ            0xC4

/****************XYZ_DATA_CFG Sensor Data Configuration Register***************/
#define HPF_OUT_MASK          0x10    // MMA8451 and MMA8452 only
#define FS1_MASK              0x02
#define FS0_MASK              0x01
#define FS_MASK               0x03

#define FULL_SCALE_2G         0x00
#define FULL_SCALE_4G         (FS0_MASK)
#define FULL_SCALE_8G         (FS1_MASK)


/************HP_FILTER_CUTOFF High Pass Filter Register **********************/
#define PULSE_HPF_BYP_MASK    0x20
#define PULSE_LPF_EN_MASK     0x10
#define SEL1_MASK             0x02
#define SEL0_MASK             0x01
#define SEL_MASK              0x03

/*************PL_STATUS Portrait/Landscape Status Register *******************/
#define NEWLP_MASK            0x80
#define LO_MASK               0x40
#define LAPO1_MASK            0x04
#define LAPO0_MASK            0x02
#define BAFRO_MASK            0x01
#define LAPO_MASK             0x06


/************** PL_CFG Portrait/Landscape Configuration Register***************/
#define DBCNTM_MASK           0x80
#define PL_EN_MASK            0x40

/*****PL_BF_ZCOMP Back/Front and Z Compensation Register***********************/

#define BKFR1_MASK            0x80
#define BKFR0_MASK            0x40
#define ZLOCK2_MASK           0x04
#define ZLOCK1_MASK           0x02
#define ZLOCK0_MASK           0x01
#define BKFR_MASK             0xC0
#define ZLOCK_MASK            0x07

/************PL_P_L_THS Portrait to Landscape Threshold Register***************/
#define PL_P_L_THS_REG        0x14

#define P_L_THS4_MASK         0x80
#define P_L_THS3_MASK         0x40
#define P_L_THS2_MASK         0x20
#define P_L_THS1_MASK         0x10
#define P_L_THS0_MASK         0x08
#define HYS2_MASK             0x04
#define HYS1_MASK             0x02
#define HYS0_MASK             0x01
#define P_L_THS_MASK          0xF8
#define HYS_MASK              0x07

/********************FF_MT_CFG Freefall and Motion Configuration Register******/
#define FF_MT_CFG_REG         0x15

#define ELE_MASK              0x80
#define OAE_MASK              0x40
#define ZEFE_MASK             0x20
#define YEFE_MASK             0x10
#define XEFE_MASK             0x08

/**********FF_MT_SRC Freefall and Motion Source Registers**********************/
#define FF_MT_SRC_REG         0x16

#define EA_MASK               0x80
#define ZHE_MASK              0x20
#define ZHP_MASK              0x10
#define YHE_MASK              0x08
#define YHP_MASK              0x04
#define XHE_MASK              0x02
#define XHP_MASK              0x01

/*****FF_MT_THS Freefall and Motion Threshold Registers*********************/
#define FT_MT_THS_REG         0x17
#define TRANSIENT_THS_REG     0x1F

#define DBCNTM_MASK           0x80
#define THS6_MASK             0x40
#define THS5_MASK             0x20
#define THS4_MASK             0x10
#define THS3_MASK             0x08
#define THS2_MASK             0x04
#define TXS1_MASK             0x02
#define THS0_MASK             0x01
#define THS_MASK              0x7F


/********FF_MT_COUNT Freefall Motion Count Registers************************/
#define FF_MT_COUNT_REG       0x18

/****************TRANSIENT_CFG Transient Configuration Register****************/

#define TELE_MASK             0x10
#define ZTEFE_MASK            0x08
#define YTEFE_MASK            0x04
#define XTEFE_MASK            0x02
#define HPF_BYP_MASK          0x01

/***********TRANSIENT_SRC Transient Source Register****************************/

#define TEA_MASK              0x40
#define ZTRANSE_MASK          0x20
#define Z_TRANS_POL_MASK      0x10
#define YTRANSE_MASK          0x08
#define Y_TRANS_POL_MASK      0x04
#define XTRANSE_MASK          0x02
#define X_TRANS_POL_MASK      0x01


/**************************PULSE_CFG Register****************************/

#define DPA_MASK              0x80
#define PELE_MASK             0x40
#define ZDPEFE_MASK           0x20
#define ZSPEFE_MASK           0x10
#define YDPEFE_MASK           0x08
#define YSPEFE_MASK           0x04
#define XDPEFE_MASK           0x02
#define XSPEFE_MASK           0x01


/**************************PULSE_SRC Register********************************/

#define PEA_MASK              0x80
#define AXZ_MASK              0x40
#define AXY_MASK              0x20
#define AXX_MASK              0x10
#define DPE_MASK              0x08
#define POLZ_MASK             0x04
#define POLY_MASK             0x02
#define POLX_MASK             0x01

#define PTHS_MASK             0x7F

/***************CTRL_REG1 System Control 1 Register****************************/
#define ASLP_RATE1_MASK       0x80
#define ASLP_RATE0_MASK       0x40
#define DR2_MASK              0x20
#define DR1_MASK              0x10
#define DR0_MASK              0x08
#define LNOISE_MASK           0x04
#define FREAD_MASK            0x02
#define ACTIVE_MASK           0x01
#define ASLP_RATE_MASK        0xC0
#define DR_MASK               0x38

#define ASLP_RATE_20MS        0x00
#define ASLP_RATE_80MS        (ASLP_RATE0_MASK)
#define ASLP_RATE_160MS       (ASLP_RATE1_MASK)
#define ASLP_RATE_640MS       (ASLP_RATE1_MASK+ASLP_RATE0_MASK)

#define ASLP_RATE_50HZ        (ASLP_RATE_20MS)
#define ASLP_RATE_12_5HZ      (ASLP_RATE_80MS)
#define ASLP_RATE_6_25HZ      (ASLP_RATE_160MS)
#define ASLP_RATE_1_56HZ      (ASLP_RATE_640MS)

#define HYB_ASLP_RATE_25HZ        (ASLP_RATE_20MS)
#define HYB_ASLP_RATE_6_25HZ      (ASLP_RATE_80MS)
#define HYB_ASLP_RATE_1_56HZ      (ASLP_RATE_160MS)
#define HYB_ASLP_RATE_0_8HZ       (ASLP_RATE_640MS)

#define DATA_RATE_1250US      0x00
#define DATA_RATE_2500US      (DR0_MASK)
#define DATA_RATE_5MS         (DR1_MASK)
#define DATA_RATE_10MS        (DR1_MASK+DR0_MASK)
#define DATA_RATE_20MS        (DR2_MASK)
#define DATA_RATE_80MS        (DR2_MASK+DR0_MASK)
#define DATA_RATE_160MS       (DR2_MASK+DR1_MASK)
#define DATA_RATE_640MS       (DR2_MASK+DR1_MASK+DR0_MASK)

#define DATA_RATE_800HZ       (DATA_RATE_1250US)
#define DATA_RATE_400HZ       (DATA_RATE_2500US)
#define DATA_RATE_200HZ       (DATA_RATE_5MS)
#define DATA_RATE_100HZ       (DATA_RATE_10MS)
#define DATA_RATE_50HZ        (DATA_RATE_20MS)
#define DATA_RATE_12_5HZ      (DATA_RATE_80MS)
#define DATA_RATE_6_25HZ      (DATA_RATE_160MS)
#define DATA_RATE_1_56HZ      (DATA_RATE_640MS)

#define HYB_DATA_RATE_400HZ   (DATA_RATE_1250US)
#define HYB_DATA_RATE_200HZ   (DATA_RATE_2500US)
#define HYB_DATA_RATE_100HZ   (DATA_RATE_5MS)
#define HYB_DATA_RATE_50HZ    (DATA_RATE_10MS)
#define HYB_DATA_RATE_25HZ    (DATA_RATE_20MS)
#define HYB_DATA_RATE_6_25HZ  (DATA_RATE_80MS)
#define HYB_DATA_RATE_3_15HZ  (DATA_RATE_160MS)
#define HYB_DATA_RATE_0_8HZ   (DATA_RATE_640MS)

#define ACTIVE                (ACTIVE_MASK)
#define STANDBY               0x00

/***************CTRL_REG2 System Control 2 Register****************************/
#define CTRL_REG2             0x2B

#define ST_MASK               0x80
#define RST_MASK              0x40
#define SMODS1_MASK           0x10
#define SMODS0_MASK           0x08
#define SLPE_MASK             0x04
#define MODS1_MASK            0x02
#define MODS0_MASK            0x01
#define SMODS_MASK            0x18
#define MODS_MASK             0x03

#define SMOD_NORMAL           0x00
#define SMOD_LOW_NOISE        (SMODS0_MASK)
#define SMOD_HIGH_RES         (SMODS1_MASK)
#define SMOD_LOW_POWER        (SMODS1_MASK+SMODS0_MASK)

#define MOD_NORMAL            0x00
#define MOD_LOW_NOISE         (MODS0_MASK)
#define MOD_HIGH_RES          (MODS1_MASK)
#define MOD_LOW_POWER         (MODS1_MASK+MODS0_MASK)


/***************CTRL_REG3 System Control 3 Register****************************/
#define FIFO_GATE_MASK        0x80    
#define WAKE_TRANS_MASK       0x40
#define WAKE_LNDPRT_MASK      0x20
#define WAKE_PULSE_MASK       0x10
#define WAKE_FF_MT_MASK       0x08
#define IPOL_MASK             0x02
#define PP_OD_MASK            0x01

/***************CTRL_REG4 System Control 4 Register****************************/
#define INT_EN_ASLP_MASK      0x80
#define INT_EN_FIFO_MASK      0x40  
#define INT_EN_TRANS_MASK     0x20
#define INT_EN_LNDPRT_MASK    0x10
#define INT_EN_PULSE_MASK     0x08
#define INT_EN_FF_MT_MASK     0x04
#define INT_EN_DRDY_MASK      0x01

/***************CTRL_REG5 System Control 5 Register****************************/
#define INT_CFG_ASLP_MASK     0x80
#define INT_CFG_FIFO_MASK     0x40
#define INT_CFG_TRANS_MASK    0x20
#define INT_CFG_LNDPRT_MASK   0x10
#define INT_CFG_PULSE_MASK    0x08
#define INT_CFG_FF_MT_MASK    0x04
#define INT_CFG_DRDY_MASK     0x01

/*
**  XYZ Offset Correction Registers
*/
#define OFF_X_REG             0x2F
#define OFF_Y_REG             0x30
#define OFF_Z_REG             0x31

/*
**  MAG CTRL_REG1 System Control 1 Register
*/
#define M_ACAL_MASK           0x80
#define M_RST_MASK            0x40
#define M_OST_MASK            0x20
#define M_OSR2_MASK           0x10
#define M_OSR1_MASK           0x08
#define M_OSR0_MASK           0x04
#define M_HMS1_MASK           0x02
#define M_HMS0_MASK           0x01
#define M_OSR_MASK            0x1C
#define M_HMS_MASK            0x03

//OSR Selections
#define M_OSR_1_56_HZ         0x00
#define M_OSR_6_25_HZ         M_OSR0_MASK
#define M_OSR_12_5_HZ         M_OSR1_MASK
#define M_OSR_50_HZ           M_OSR1_MASK+M_OSR0_MASK
#define M_OSR_100_HZ          M_OSR2_MASK
#define M_OSR_200_HZ          M_OSR2_MASK+M_OSR0_MASK
#define M_OSR_400_HZ          M_OSR2_MASK+M_OSR1_MASK
#define M_OSR_800_HZ          M_OSR2_MASK+M_OSR1_MASK+M_OSR0_MASK

//Hybrid Mode Selection
#define ACCEL_ACTIVE          0x00
#define MAG_ACTIVE            M_HMS0_MASK
#define HYBRID_ACTIVE         (M_HMS1_MASK | M_HMS0_MASK)

/*
**  MAG CTRL_REG2 System Control 2 Register
*/

#define M_HYB_AUTOINC_MASK    0x20
#define M_MAXMIN_DIS_MASK     0x10
#define M_MAXMIN_DIS_THS_MASK 0x08
#define M_MAXMIN_RST_MASK     0x04
#define M_RST_CNT1_MASK       0x02
#define M_RST_CNT0_MASK       0x01

//Mag Auto-Reset De-Gauss Frequency
#define RST_ODR_CYCLE         0x00
#define RST_16_ODR_CYCLE      M_RST_CNT0_MASK
#define RST_512_ODR_CYCLE     M_RST_CNT1_MASK
#define RST_DISABLED          M_RST_CNT1_MASK+M_RST_CNT0_MASK

/*
**  MAG CTRL_REG3 System Control 3 Register
*/

#define M_RAW_MASK            0x80
#define M_ASLP_OS_2_MASK      0x40
#define M_ASLP_OS_1_MASK      0x20
#define M_ASLP_OS_0_MASK      0x10
#define M_THS_XYZ_MASK        0x08
#define M_ST_Z_MASK           0x04
#define M_ST_XY1_MASK         0x02
#define M_ST_XY0_MASK         0x01
#define M_ASLP_OSR_MASK       0x70
#define M_ST_XY_MASK          0x03

//OSR Selections
#define M_ASLP_OSR_1_56_HZ    0x00
#define M_ASLP_OSR_6_25_HZ    M_ASLP_OS_0_MASK
#define M_ASLP_OSR_12_5_HZ    M_ASLP_OS_1_MASK
#define M_ASLP_OSR_50_HZ      M_ASLP_OS_1_MASK+M_ASLP_OS_0_MASK
#define M_ASLP_OSR_100_HZ     M_ASLP_OS_2_MASK
#define M_ASLP_OSR_200_HZ     M_ASLP_OS_2_MASK+M_ASLP_OS_0_MASK
#define M_ASLP_OSR_400_HZ     M_ASLP_OS_2_MASK+M_ASLP_OS_1_MASK
#define M_ASLP_OSR_800_HZ     M_ASLP_OS_2_MASK+M_ASLP_OS_1_MASK+M_ASLP_OS_0_MASK

/*
**  MAG INT SOURCE Register
*/
#define M_INT_SOURCE          0x5E

#define SRC_M_DRDY_MASK       0x04
#define SRC_M_VECM_MASK       0x02
#define SRC_M_THS_MASK        0x01

/*
**  ACCEL VECTOR CONFIG Register
*/

#define A_VECM_INIT_CFG_MASK  0x40
#define A_VECM_INIT_EN_MASK   0x20
#define A_VECM_WAKE_EN_MASK   0x10
#define A_VECM_EN_MASK        0x08
#define A_VECM_UPDM_MASK      0x04
#define A_VECM_INITM_MASK     0x02
#define A_VECM_ELE_MASK       0x01

/*
**  ACCEL VECTOR THS MSB AND LSB Register
*/

#define A_VECM_DBCNTM_MASK    0x80

/*
**  MAG VECTOR CONFIG Register
*/

#define M_VECM_INIT_CFG_MASK  0x40
#define M_VECM_INIT_EN_MASK   0x20
#define M_VECM_WAKE_EN_MASK   0x10
#define M_VECM_EN_MASK        0x08
#define M_VECM_UPDM_MASK      0x04
#define M_VECM_INITM_MASK     0x02
#define M_VECM_ELE_MASK       0x01

/*
**  MAG VECTOR THS MSB AND LSB Register
*/

#define M_VECM_DBCNTM_MASK    0x80

/*
**  ACCEL FFMT THS X MSB AND LSB Register
*/

#define A_FFMT_THS_XYZ_EN_MASK 0x80
#define A_FFMT_THS_X_LSB_MASK  0xFC

/*
**  ACCEL FFMT THS Y MSB AND LSB Register
*/

#define A_FFMT_THS_Y_EN_MASK 0x80
#define A_FFMT_THS_Y_LSB_MASK  0xFC

/*
**  ACCEL FFMT THS Z MSB AND LSB Register
*/

#define A_FFMT_THS_Z_EN_MASK        0x80
#define A_FFMT_THS_Z_LSB_MASK       0xFC

#define FXOS8700CQ_WHOAMI_VAL   0xC7        // FXOS8700CQ WHOAMI production register value
#define FXOS8700CQ_READ_LEN     12          // 6 channels of two bytes = 12 bytes 
#define UINT14_MAX              16383       // For processing the accelerometer data to right-justified 2's complement

/***************************TYPES*********************************/

typedef enum mode_t {DISABLED=0x00,
                        BUFFER=0x01,
                        OVERFLOW=0x10,
                        TRIGGERED=0x11} mode_t;
                    
typedef enum range_t {SCALE2G=0x00,
                        SCALE4G=0x01,
                        SCALE8G=0x10} range_t;


typedef enum ACC_orientation_t{PORT_UP_FRONT = 0,
                            PORT_UP_BACK,
                            PORT_DOWN_FRONT,
                            PORT_DOWN_BACK,
                            LAND_LEFT_FRONT,
                            LAND_LEFT_BACK,
                            LAND_RIGHT_FRONT,
                            LAND_RIGHT_BACK } ACC_orientation_t;

typedef struct rawdata {
    int16_t x;  
    int16_t y;  
    int16_t z;  
} rawdata_t;

void            FXOS8700CQ_Initialize(void);
char            FXOS8700CQ_ReadStatusReg(void);
void            FXOS8700CQ_ActiveMode(void);
char            FXOS8700CQ_StandbyMode(void);
void            FXOS8700CQ_HybridMode(void);
char            FXOS8700CQ_GetChipMode(void);
char            FXOS8700CQ_ID (void);

void            FXOS8700CQ_ConfigureAccelerometer(void);
void            FXOS8700CQ_PollAccelerometer (rawdata_t *accel_data);
void            FXOS8700CQ_HighPassFilter(char status);
void            FXOS8700CQ_FullScaleRange(range_t range);
void            FXOS8700CQ_SetAccelerometerDynamicRange(range_t range);

void            FXOS8700CQ_ConfigureMagnetometer(void);
void            FXOS8700CQ_PollMagnetometer (rawdata_t *mag_data);
char            FXOS8700CQ_MagnetometerStatus(void);

void            FXOS8700CQ_GetData(rawdata_t *accel_data, rawdata_t *magn_data);

void            FXOS8700CQ_FIFOMode(mode_t mode);
void            FXOS8700CQ_SetODR (char DataRateValue);
char            FXOS8700CQ_GetODR (void);
char            FXOS8700CQ_GetTemperature(void);

char            FXOS8700CQ_GetOrientation(void);
void            FXOS8700CQ_ConfigureOrientation(void);
void            FXOS8700CQ_ConfigureGenericTapMode(void);
void            FXOS8700CQ_ConfigureSingleTapMode(void);
void            FXOS8700CQ_ConfigureDoubleTapMode(void);

void            FXOS8700CQ_WriteByte(char reg, char value);
void            FXOS8700CQ_WriteByteArray(char reg, char* buffer, char value);
char            FXOS8700CQ_ReadByte(char reg);
void            FXOS8700CQ_ReadByteArray(char reg, char *buffer, unsigned int length);

#endif